[designLines AI & Big Data Designline](https://www.eetimes.com/designline/ai-big-data-designline/) # RISC-V Is Inevitable, State of the Union Keynote Argues ## RVA23 silicon fuels rise of RISC-V in server applications. [Pablo Valerio](https://www.eetimes.com/author/pablo-valerio/) ### Sha

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RISC-V Is Inevitable, State of the Union Keynote Argues

RVA23 silicon fuels rise of RISC-V in server applications.

Pablo Valerio

Arrival of server-class silicon and the RVA23 standard

For years, the technology sector has anticipated the moment when RISC-V would break into the data center. According to Asanović, that moment has arrived. “We’re on this widespread adoption in application processors, and I think one of the themes of the summit this year here in Europe is you’re starting to see the promise of high-performance RVA23 silicon actually appearing,” Asanović told the keynote audience. “The server-class system is actually starting to appear, and I think that’s the theme for 2026.”

The RVA23 standard, officially approved in October 2024, is at the heart of this move into enterprise. It brings hardware developers and software engineers together under a common framework.

RVA23 standard

“We are already working closely with several hyperscalers and data center owners and suppliers to design these next-generation processors,” Asanović told EE Times in an email conversation after the event. “They are investing in RISC-V as an alternative to the incumbent architectures as it provides much greater flexibility, both in technical features and in the business model, and there is no barrier to providing dominant performance in this space.”

This alignment allows developers to test their software directly on real hardware instead of using emulators, representing a big step forward for the standard. “One big takeaway is that the community has agreed that RVA23 is the basis of these platforms,” Asanović said during his presentation. “The software ecosystem should be happy that people have come together, and that’s the one thing we should have. It’s not only the RVA23 profile, but it’s also the server platform spec, which includes many more of the features you need to make a real server and support frameworks.”

Optimization guidance

Entering the server market takes more than just basic features—it demands top-tier performance. To help close the gap between simple software compatibility and real competitive performance, Asanović introduced a new idea during his keynote: optimization guidance options.

In the past, RISC-V ISA strings only described what an instruction did, not how fast it should execute. This sometimes caused slowdowns, such as when hardware makers used slow “trap-and-emulate” methods for misaligned memory accesses.

To fix this, new options such as Oilsm and Ovlt will set clear performance standards. For example, Oilsm allows software to assume that misaligned scalar and vector accesses will be handled quickly by hardware, so there is no need for complicated software fixes.

Oilsm

“The point of these optimization guidance options is to align hardware and software on performance expectations for features in the architecture,” Asanović said. “This also tells the hardware vendors, if you want to be competitive, you better support this in hardware because the software is going to assume this is how it works.”

When EE Times asked whether these guidelines leave too much wiggle room for hardware vendors to cut corners, Asanović was definitive. “No, the optimization guidance options are not just suggestions, but inform the software ecosystem that they only need to optimize code for high-performance implementations,” he wrote in a follow-up email conversation. “Unlike legacy architectures, RISC-V encourages competition among suppliers. Vendors that do not provide competitive performance will not be successful… and in this way, the optimization guidance options raise the bar on achievable RISC-V performance.”

AI and the “Wheel of Reincarnation”

As generative AI reshapes computing demands, RISC-V could capture the burgeoning AI accelerator market. During his address, Asanović referenced computer science pioneer Ivan Sutherland’s 1968 concept, the “Wheel of Reincarnation,” to explain the cyclical nature of processing architectures.

Wheel of Reincarnation

Hardware accelerators typically begin as specialized offload engines, gradually acquire general-purpose features to improve efficiency, and eventually morph into fully independent processors.

RISC-V does well in this cycle because it is naturally modular. Unlike other instruction sets, it can work smoothly as an AI Host ISA, a device-level AI ISA, or a fully self-hosted AI system that can scale down to small embedded devices. The architecture is also rapidly expanding its digital signal processing (DSP) capabilities, moving from the simple P extension for small cores to a more powerful vector DSP extension for larger tasks.

“The goal here of doing all this and making this modular, making this cover the space, is that we can share software development across all these different spaces and design choices,” Asanović noted on stage. “Because software is the highest cost.[…] but we’re trying to keep these modular and scalable to reduce our software time in training.”

Rethinking security with CHERI

Enterprise adoption necessitates enterprise-grade security. The RISC-V International consortium is rapidly advancing a suite of new security extensions, including supervisor physical memory protection (SPMP), IOPMP for embedded device security, and supervisor domains to facilitate confidential computing.

The biggest security change Asanović discussed was the Capability Hardware Enhanced RISC Instructions (CHERI). CHERI is built to give detailed memory safety and reduce software vulnerabilities directly in hardware, marking a major change in how the architecture is designed. Instead of adding CHERI as a standard extension, it has been created as an entirely new base ISA: RV32Y and RV64Y.

Capability Hardware Enhanced RISC Instructions

“CHERI is not an extension; CHERI is a new base,” Asanović clarified to the keynote audience. “This gives a nice place to sit in that RISC-V framework without disturbing the other part, so the CHERI folks can innovate without being constrained by the other parts of the architecture.”

Addressing concerns that creating a new base ISA might fracture the open-source community, Asanović offered a devoted defense to EE Times. “CHERI is too invasive to be a simple extension on regular RISC-V, and so needs a new base ISA for that reason,” he argued. “The CHERI developers have already taken this approach to reuse almost all of the existing RISC-V ISA definitions unchanged, and intend to continue tracking new RISC-V extensions and supporting them under CHERI, so CHERI will not be developing a parallel incompatible set of ISA extensions… with RISC-V CHERI there will now be a single global open standard for CHERI systems”.

Microcontroller diversity

While RISC-V moves into cloud servers, its leaders are also improving its core strength in microcontrollers. Because the architecture is open, embedded developers have been able to remove extra features to save space, but this has sometimes risked breaking up the ecosystem. To avoid software fragmentation, the community is completing the RVM ISA profile and making key features such as fast interrupts, nested protection, and trace support standard for microcontrollers.

During his keynote, Asanović offered a stern word of guidance to engineers obsessed with stripping away core features for marginal silicon savings. “Often, people are sort of fixated on saving a gate or two or three by losing the big picture,” he warned the audience. “Having too many options means you don’t have a profile, you don’t have a standard, you just have a bunch of options. We already have that. The whole point of the standard here is to set a set of mandated features everybody can rely on.”

Expanding on this philosophy with EE Times, Asanović rejected the notion that standardization inherently leads to bloat, characterizing the argument as a false dichotomy. “Sockets that need extreme specialization are obviously not concerned with fragmentation. Sockets that need software compatibility cannot allow extreme specialization,” he wrote to EE Times. “Moving to RISC-V vastly reduces complexity and fragmentation when compared with the dozens of completely different legacy ISAs that currently exist in different types of processor on an SoC or in a system.”

Inevitable RISC-V future

Challenging legacy ISAs in the data center is a huge task that will take several generations of technology. The main obstacle to better performance is now economic, not just technical. It needs a healthy cycle between hardware supply and developer demand.

Yet, the tone of the RISC-V Europe Summit 2026 was one of supreme confidence. The delivery of high-performance RVA23 silicon this year serves as a historic inflection point.

“It’s not just about replacing existing general-purpose systems,” Asanović concluded at the end of his keynote. “RISC-V gives you this unique opportunity to innovate and handle many different workloads, but in all new ways, all with a standard framework underpinning it and no barrier to you trying things out.”

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RISC-V Is Inevitable: State of the Union Keynote Argues